1. Field of the Invention
The present invention relates to a voltage regulator, more particularly to a low dropout voltage regulator with an improved voltage controlled current source.
2. Description of Related Art
Voltage regulators with low dropout (LDO) are widely used in power management systems of PC motherboards, notebooks computers, mobile phones, and many other products. As a voltage supply, the LDO voltage regulator demonstrates many advantages in the field. Perfect line and load regulation, high power supply rejection ratio (PSRR), fast response, very small quiescent current, and low noise make the LDO voltage regulator irreplaceable. Stabilizing the LDO voltage regulator with 1 uF low ESR (equivalent series resistance) ceramic capacitor under a large output current is still a challenge.
FIG. 1 shows a typically conventional LDO voltage regulator 100 with a compensation voltage controlled current source (VCCS). The specific description to the conventional LDO voltage regulator may be referred in a reference entitled “A Frequency Compensation Scheme for LDO Voltage Regulators”, invented by Chaitanya K. Chava and Jose Silva-Martinez, published on IEEE J. Solid-State Circuits, vol. 51, pp. 1041-1050, June 2004, which is hereby incorporated by reference.
The LDO voltage regulator 100 comprises a differential amplifier circuit 102, an intermediate amplifier circuit 104, an output pass circuit 106, a feedback circuit 108 and a voltage controlled current source (VCCS) 110. These circuits are intercoupled to form a voltage negative feedback loop.
The differential amplifier circuit 102 includes a differential amplifier gm1, a resistor R1 and a capacitor C1 coupled in parallel between an output terminal of the differential amplifier gm1 and a ground reference. The resistor R1 and the capacitor C1 may be an equivalent series resistance (ESR) and an equivalent series capacitance (ESC) of the differential amplifier circuit, respectively.
The intermediate amplifier circuit 104 includes an amplifier gm2 a resistor R2 and a capacitor C2 coupled in parallel between an output terminal of the amplifier gm2 and the ground reference. An input terminal of the amplifier gm2 is coupled to the output terminal of the differential amplifier gm1. The resistor R2 and the capacitor C2 may be the ESR and the ESC of the intermediate amplifier circuit, respectively.
The output pass circuit gm3 106 includes a pass transistor MPass and an output capacitor Co. The pass transistor MPass is usually a P-type MOS field effect transistor. A control terminal of the pass transistor MPass such as a gate electrode of the MOS transistor is coupled to the output terminal of the amplifier gm2. An input terminal of the pass transistor MPass such as a source electrode of the MOS transistor is coupled to a power supply Vcc. An output voltage Vout is leaded from an output terminal of the pass transistor MPass such as a drain electrode of the MOS transistor. The output capacitor Co and a resistor RL representative of a load are coupled in parallel between the output voltage Vout and the ground reference.
The feedback circuit 108 includes a pair of ladder resistors Rf1 and Rf2 coupled in series between the output voltage Vout and the ground reference. One terminal of the resistor Rf1 is coupled to the output terminal of the pass transistor MPass. A middle node B between the resistor Rf1 and the resistor Rf2 is coupled to an input terminal of the differential amplifier gm1 for feedback. Another input terminal of the differential amplifier is coupled to a predetermined reference voltage.
An input terminal of the VCCS 110 is coupled to a node A between the pass transistor and the feedback circuit, and an output terminal of the voltage controlled current source circuit is coupled to the node B. The VCCS 110 is designed for outputting a constant current into the node B depending on a voltage of the input terminal thereof. The VCCS 110 includes a NMOS transistor MN1, a current mirror, a first current source I1, a second current source I2 and a compensation capacitor CC. A gate electrode of the MN1 serves as the input terminal of the VCCS, a drain electrode of the MN1 is coupled to an input terminal of the current mirror and a source electrode of the MN1 is coupled to a terminal of the first current source I1. The other terminal of the first current source I1 is grounded. One terminal of the compensation capacitor CC is coupled to the source electrode of the MN1, and the other terminal of the compensation capacitor CC is grounded. One terminal of the second current source I2 is grounded, and the other terminal of the second current source I2 serves as the output terminal of the VCCS 110. An output terminal of the current mirror is coupled to the output terminal of the VCCS 110.
A small signal transfer function of the VCCS 110 is shown below:
                                          I            fb                                V            O                          =                              SC            C                                1            +                                          SC                C                                            gm                                  MN                  ⁢                                                                          ⁢                  1                                                                                        (        1        )            where Ifb denotes an output current of VCCS, VO denotes a control voltage of the VCCS namely the output voltage Vout, SCC denotes a conductance of the compensation capacitor CC and gmMN1 denotes a transconductance between the drain and source electrodes of the MN1.
A minimum operating supply voltage for the LDO voltage regulator is Vdrop—I1 +Vdrop—CurrentMirror+Vdsat—MN1, wherein Vdrop—I1 denotes a dropout voltage on the first current source I1, Vdrop—CurrentMirror denotes a dropout voltage on the current mirror and Vdsat—MN1 denotes a saturated dropout voltage between the drain and source electrodes of the MN1. A minimum output voltage of the LDO voltage regulator is Vth—MN1+Vdrop—I1, wherein Vth—MN1 denotes a threshold voltage of the MN1.
In the standard CMOS, a body effect of the NMOS transistor can't be neglected. Usually, the NMOS transistor is formed on a substrate thereof directly. In FIG. 1, the body effect of the MN1 may degrade its performance. If the body effect is considered, the equation (1) may become:
                                          I            fb                                V            O                          =                              SC            C                                1            +                                          SC                C                                            (                                                      gm                                          MN                      ⁢                                                                                          ⁢                      1                                                        -                                      gmb                                          MN                      ⁢                                                                                          ⁢                      1                                                                      )                                                                        (        2        )            An item gmbMN1 which denotes a body effect conductance of the MN1 is added.
The minimum output voltage of the LDO voltage regulator is adversely affected because the threshold voltage of the MN1 Vth—MN1 has a relation to the body effect of the MN1 according to following equation.Vth—MN1=Vth0+γ(√{square root over (VSB+2φF|)}−√{square root over (|2φF|)})  (3)where Vth0 denotes an intrinsic threshold voltage of the MN1, γ denotes a body effect constant, VSB denotes a dropout voltage between the source electrode and the substrate of the MN1 and φF denotes a fermi potential. The threshold voltage of the MN1 Vth—MN1 may become higher because the dropout voltage VSB is larger than zero, thereby the minimum output voltage can't be low enough. This should limit the applications of the LDO voltage regulator.
The LDO voltage regulator is mainly used to supply power for system level chips. With the size of system level chips gradually being reduced, supply voltages required by the system level chips are reduced in proportion. Hence, the LDO voltage regulator is required to operate with the low input voltage and the low output voltage. In some cases, the output voltage of the LDO voltage regulator may be 1.2V or more lower, and the input voltage of the LDO voltage regulator may be 2V or more lower.
However, the threshold voltage Vth of the NMOS transistor in standard CMOS process commonly is 0.7V˜1.1V and can't be adjusted. Furthermore, a maximum technical error 1.0V should be considered usually. The dropout voltage Vdrop—I1 commonly is 0.4˜0.8V since it is twice of the saturated dropout voltage Vdsat, which is 0.2˜0.4V, between the gate and source electrodes of the NMOS transistor in standard CMOS process. Hence, the minimum output voltage Vth—MN1+Vdrop—I1 of the LDO voltage regulator shown in FIG. 1 may be higher than 1.5V. At the same time, the dropout voltage Vdrop—CurrentMirror on the current mirror is approximately equal to Vdsat+Vth, thereby the minimum operating supply voltage Vdrop—I1+Vdrop—CurrentMirror+Vdsat—MN1 for the LDO voltage regulator may be higher than 1.9V. As a result, the conventional LDO voltage regulator may not completely satisfy the low input/output voltage requirements.
Thus, there is a need for LDO voltage regulators with an improved VCCS to overcome the above disadvantages.